Control circuit for a centrex attendant console interface

Abstract

A control circuit for effecting the transfer of data messages between an interface circuit and a CENTREX equipped central office exchange. The central office exchange includes a peripheral processor and the interface circuit includes an input and an output sequential memory for receiving and sending respectively, data messages to the peripheral processor. An input control circuit includes a first gating means having inputs connected to the peripheral processor and which produces an output signal responsive to the simultaneous application of a first and a second control signal. First bistable memory means receives the gating means output signal and further includes a clock input connected to a write select signal from the peripheral processor. Responsive to the write select signal, the gating means output signal is stored in the first bistable memory means. Second bistable memory means connected to the first bistable memory means output includes a clock input connected to a source of clocking signals. During the rising edge of the clocking signal the second bistable memory means outputs a signal which is combined with an input enabling signal from the peripheral processor by a second gating means to produce a shift-in signal for the input sequential memory. An output control circuit is substantially similar to the first control circuit with the exception of the use of a read select signal instead of a write select signal by the first bistable memory means. An output enable signal is used with the second bistable memory means output to produce a shift-out signal for the output sequential memory.