The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 1987

Filed:

Jan. 30, 1985
Applicant:
Inventors:

William H Slavik, Palos Hills, IL (US);

William P Carlson, Hanover Pk., IL (US);

George L Cepynsky, Woodridge, IL (US);

Paul G Dussault, Barrington, IL (US);

Steven E Margison, Downers Grove, IL (US);

James A Wolf, Jr, Deerfield, IL (US);

Assignee:

Nuvatec, Inc., Downers Grove, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09B / ;
U.S. Cl.
CPC ...
434335 ; 434322 ; 434327 ; 434362 ;
Abstract

A data entry terminal for storing a plurality of user generated answers is described which includes a removable volatile read/write memory module. The memory module is used to store formatting information used to configure the data entry terminal as appropriate for a particular set of questions. The memory module can for example store a set of correct answers as well as a set of user answers for each of the questions of the test, and it can store data used to disable certain functions of the data entry terminal, such as the ability of a user to revise an initially entered answer. The data entry terminal operates to record user answers in the portable memory module, which can then be removed from the data entry terminal and applied as an input to an external computer for analyzing user responses. The portable memory module includes a battery for powering a volatile semiconductor memory included in the module. The semiconductor memory is shielded against static discharge, and one of the chip enable terminals of the memory is coupled to a capacitor to prevent momentary voltage transients from changing the contents of the memory in an uncontrolled fashion.


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