The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 1987

Filed:

Apr. 14, 1986
Applicant:
Inventors:

Meera Vijan, Troy, MI (US);

John C McGill, Rochester, MI (US);

Paul N Day, Troy, MI (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; B44C / ; C03C / ; C23F / ;
U.S. Cl.
CPC ...
156643 ; 29580 ; 148-15 ; 156646 ; 156649 ; 156652 ; 156656 ; 156657 ; 1566591 ; 156662 ; 20419232 ; 357-4 ; 357 56 ; 427 39 ;
Abstract

Thin film semiconductor devices such as amorphous silicon alloy p-i-n diodes and the like which utilize mesa-like semiconductor structures having vertical sidewalls are formed by a process which eliminates overhangs and neutralizes contaminants on the sidewalls that can result in short circuits or degradation of device performance. Smooth vertical sidewalls free of overhangs and voids are created by: successively depositing the desired semiconductor layers on a substrate, then depositing and patterning a top metal contact mask on the semiconductor layers, followed by removing the unwanted portions of the semiconductor layers by reactive ion etching. The disclosed reactive ion etching provides controlled vertical etching with virtually no lateral etching, thereby providing smooth sidewalls. The top metal contact mask protects the underlying semiconductor layers during the anisotropic etching process, and its edges are precisely aligned with the sidewalls of the underlying semiconductor layers that define the mesa structure when the etching is complete. The top metal contact mask which is formed by conventional deposition and patterning techniques, serves as a connection between the metal electrode which connects semiconductor layers of the mesa structure to the top metallization which is patterned to define desired interconnections. Ion damage and contaminants formed on the sidewalls during etching are removed or neutralized by contacting the sidewalls with a base solution and/or annealing the mesa structure before it is covered with an insulation layer.


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