Two-speed clock scheme for co-processors

Abstract

The present invention relates to a method and apparatus for a system utilizing a microprocessor having a faster maximum operating frequency and a numeric data processor having a slower maximum operating frequency which runs the system at the lower clocking frequency only during those times when both the microprocessor and the numeric data processor are required to perform processing functions and runs the system at the higher clocking frequency when only the microprocessor is required. Therefore the method and apparatus of the invention provides greater operating efficiency for the microprocessor, while not sacrificing the interface capabilities of the numeric data processor. In the apparatus of the present invention, the clocking frequencies are generated by a clocking generator which is coupled to both the microprocessor and the numeric data processor. The generator responds to signals from a control source to provide either the faster or the slower clocking frequency. The control source is responsive to program command such that it produces a first signal when the program does not require a numeric data processor to preform its processing functions and produces a second signal when the program requires te numeric data processor to perform its functions. In addition, a second signal from the source operates the reset of te numeric data processor.