The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 1987
Filed:
Aug. 16, 1984
Klye L Burson, Indianapolis, IN (US);
Scott O Campbell, Indianapolis, IN (US);
Apparajan Ganesan, Indianapolis, IN (US);
Ronald A Morrison, Indianapolis, IN (US);
American Telephone and Telegraph Company, AT&T Technologies Inc., Murray Hill, NJ (US);
Abstract
A voltage comparator (10) includes two sampled input networks connected in arallel between an input reference voltage (Vref) and the inverting input (16) of an integrator (12,14), the other input (18) of which is grounded. The first input network has a first input capacitor (C1) which is through-switched at a first sampling frequency (F1). The second input network has a second input capacitor which is diagonally-switched at a second sampling frequency (F2), thus providing an output voltage to the integrator (12,14) which is of opposite polarity to that of the first network. For a given ratio between the capacitors (C1,C2), the output (15) of the integrator is determined by the relationship between the sampling frequencies (F1,F2), thus providing a comparator capability. Also disclosed is a frequency lock loop (34) in which the output (Vcontrol) of a frequency comparator (38) is filtered of the switching frequencies and utilized as the control voltage for a voltage controlled oscillator (42). The output of the oscillator is then coupled to a switching pulse generator (44) which provides the switching pulses (F2,F2N) to the second input network of the comparator (38).