Emitter coupled logic to transistor transistor logic translator

Abstract

An emitter coupled logic (ECL) to transistor-transistor logic (TTL) translator is provided with a transistor clamp operatively coupled in at least one of the alternate transistor collector paths of the ECL input gate for clamping the voltage applied through the transistor collector path by the ECL current source to a level below saturation of the ECL input gate. The source current generated by the ECL current source may therefore be increased for accelerate turn-off of the TTL output gate of the translator without saturation of the ECL input gate. The transistor clamps are also applied in an ECL to tristate TTL translator in which the TTL output gate is a TTL tristate output device or buffer with dual phase splitter transistors. A dual transistor clamp arrangement in at least one of the ECL input gate transistor collector paths also provides separate clamped base drives to the dual phase splitter transistors for eliminating 'current hogging' or base drive preemption. The accelerating feedback diode of the TTL tristate output device or buffer circuit can therefore maintain the high current sinking mode proportional to .beta.2 through the pull-down transistor element for cancelling transmission line reflection during transition from high to low level potential at the output.