The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 1987

Filed:

Mar. 26, 1985
Applicant:
Inventors:

Hirohisa Shishikura, Tokyo, JP;

Ichiro Sase, Tokyo, JP;

Akio Yanagimachi, Tokyo, JP;

Osamu Yamada, Tokyo, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 37 ; 371 43 ; 371 36 ;
Abstract

An error correction system for a difference set cyclic (272,190) code with 190 data bits and 82 test bits in a coded transmission teletext system which transmits character information on the vertical blanking interval of a television signal has been improved in peripheral circuits for operating an error correction circuit. A first improvement is to correct only designated packets which are in frame synchronization condition and/or designated by an index register. A second improvement is to handle shortened (L,k) code where L is less than 272, using common hardware. A third improvement is selection of three operational modes of data to be corrected. In the first mode, uncorrected data is supplied by an external circuit, and said uncorrected data is stored temporarily in a buffer memory, and corrected data is stored in said buffer memory again to supply external circuit corrected data. Transfer of data between the buffer memory and the error correction circuit is handled by wired logic hardware apparatus. In a second mode, uncorrected data and corrected data are provided in a buffer memory but no external circuit is concerned in operation of the present system. In a third mode, no buffer memory is used, and an external circuit supplies uncorrected data to an error correction circuit directly and receives corrected data directly from the error correction circuit.


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