The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 1987
Filed:
Oct. 21, 1985
Michael J Serrone, Sunnyvale, CA (US);
Timothy P Halloran, Cupertino, CA (US);
Gary L Wagner, Menlo Park, CA (US);
Ford Aerospace & Communications Corporation, Detroit, MI (US);
Abstract
A lock detector (12) used in conjunction with a bit synchronizer (14) for determining when a random binary input signal (2) is in lock with a clock (7) generated by the bit synchronizer (14). A window comparator (3, 5; or 23, 25, 27) determines whether the amplitude of the input signal (2) is within or without an amplitude window, and generates a signal (33) as a result of said determination. This signal (33) is sampled at periodic sampling points (X, Y). The set of X sampling points and set of Y sampling points are interleaved and usually separated by half a bit period. The X samples and Y samples are averaged and compared. Means (19) are provided for declaring a lock condition when the X average exceeds the Y average by a preselected threshold (V.sub.REF), which occurs when the X points are positioned near mid-points of data bits (35) and the Y points are positioned near data transitions (39). The circuit (12) will not lock on false sidebands and can operate at very low signal-to-noise ratios.