The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 1987
Filed:
Jul. 10, 1986
Rudolph E Corwin, Seattle, WA (US);
Honeywell Inc., Minneapolis, MN (US);
Abstract
A zero insertion force connector for electrically and mechanically connecting the terminal pins of a pin grid array semiconductor device to corresponding terminal pins on a printed wiring board. The connector includes first and second identically molded plastic substrates, each having a grid pattern of apertures therethrough where the grid corresponds to the spacing of the terminal pins on the pin grid array semiconductor device. Formed proximate one end of each of the rectangular apertures is a rectangular post which projects outwardly from a major surface of the substrate and which has a height approximately equal to the thickness dimension of the substrate, such that when the first substrate is inverted relative to the second substrate, the projecting posts of one will fit into the rectangular apertures of the other. The posts are dimensioned relative to the size of the rectangular apertures such that an opening exists into which both the terminal pins on the pin grid array device and the spring pins on the printed wiring board can simultaneously fit into these openings. Completing the assembly is a frame which is made to surround the two substrates and which has an adjustment feature for clamping the edges of the substrates. When so clamped, the first substrate is moved laterally relative to the second substrate, thereby squeezing the mating terminals of the printed circuit board and pin grid array together between the projecting posts of the two substrates.