Semiconductor memory device with trench surrounding each memory cell

Abstract

A semiconductor device has memory cells respectively located at intersections of bit and word lines arranged in a matrix form, each of the memory cells being constituted by a single insulated gate transistor and a single capacitor. One memory cell is formed in an element formation region defined by each of trenches arranged in a matrix form. The capacitor has an insulating film formed along part of a side wall surface of a trench formed in at least a direction of thickness of a semiconductor substrate and a conductive layer formed along the insulating film. The transistor has a gate insulating film adjacent to the capacitor and formed along a remaining portion of the side wall surface of the trench, a gate electrode formed along the gate insulating film, and a diffusion region formed in a major surface of the semiconductor substrate which is adjacent to the gate insulating film. The semicondcutor memory device further has an isolation region between two adjacent ones of the memory cells along two adjacent ones of the bit or word lines. A method of manufacturing the semiconductor is also proposed.