The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 1987

Filed:

May. 28, 1985
Applicant:
Inventor:

Howard C Kirsch, Emmaus, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307475 ; 307443 ; 307451 ; 307585 ;
Abstract

A TTL to CMOS input buffer (20) which prevents static current flow when the TTL input signal is at a relatively low voltage logic '1' state. A transition detector (44) responsive to the input TTL logic signal and a voltage boosting circuit (50) connected between a positive power supply (VDD) and the input to a first CMOS inverter (30) are utilized to sense an input signal '0' to '1' transition and boost the TTL logic '1' signal to a voltage level which will prevent the p-channel transistor (32) included in the CMOS inverter from turning 'on'. The voltage boosting circuit will subsequently be disconnected from the input to the p-channel transistor to prevent the input from being fully charged to the positive power supply.


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