Parity integrity check logic

Abstract

A computer system includes at least on error detecting circuit for checking data bits and an associated check bit to verify that the data does not contain an error. An apparatus for verifying the operation of the error detection circuit comprises a generator unit operatively connected to said data lines for receiving data bits, for outputtting a verification signal and a check bit signal. The verification signal indicates the validity of the data bits during a read operation, and the check bit signal is generated during a write operation. A gate element having an input terminal to receive at least one check bit controls at least one input to the generator unit. A first control signal is transmitted to the generator unit thereby causing the check bit signal generated by the generator unit to be valid or invalid in response to the first control signal. Further, the check bit associated with the data is transmitted to the generator unit in response to a second control signal. The second control signal indicates the read operation is in process thereby permitting the generator unit to perform a checking operation independent from the first control signal, thereby permitting verification of the error detection circuit, the checking operation being the verification of the data during the read operation.