High-speed transient pulse height counter

Abstract

A pulse height counter for counting the number of excursions of an incoming analog signal through each of a plurality of amplitude ranges. The pulse height counter automatically records not only the number of excursions through each amplitude level, but also records the number of amplitude excursions for each of a plurality of intervals. An analog input signal to be analyzed is synchronously applied to each of a plurality of comparators (VCO - VCF), which have reference voltages that are related so as to define predetermined amplitude ranges. During a count cycle, a counting circuit (CO - CF) receives the output signals from each of the comparators and produces a set of count data that indicates the number of occurrences of the analog input signal within each of the amplitude ranges. The count cycle is followed by a write cycle, during which the count values are stored in separate data bins, or event memories (MO - MF). The addresses of the memories are related to separate intervals during which count data for individual input signals can be stored. The addresses are shared by the memories so that, for a given interval, the count data for each of the amplitude ranges are stored at the same address but in a separate one of the memories. Thus, the count data for each of the amplitude ranges recorded during a predetermined interval may be recalled and displayed (18, 20, 22) during a readout mode of operation. The timing of the counting and writing cycles of operation is controlled by a count timer (32), a write timer (34), and an address counter (38) included in a timing and control circuit (10). Upon receipt of the analog input signal, the count timer is triggered to enable transfer of the outputs of the comparators to the counters. At the conclusion of the count cycle, the comparator outputs are disabled and the memories are enabled so that the count data may be transferred thereto. At the conclusion of the write cycle, the memories are disabled from receiving further count data and the counters are automatically reset so that new count data can be created upon receipt of a subsequent input signal. Substantially simultaneously with the resetting of the counters, the commonly shared address is incremented by 1 so that the count data for the next-received input signal is stored in the respective memories at the next successive storage location.