The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 1987
Filed:
Jan. 23, 1986
Neng-Haung Sheng, Thousand Oaks, CA (US);
Mau-Chung F Chang, Thousand Oaks, CA (US);
Chien-Ping Lee, Pasadena, CA (US);
Rockwell International Corporation, El Segundo, CA (US);
Abstract
A method is disclosed which is capable of producing improved field effect transistors such as high electron mobility transistors and metal semiconductor field effect transistors. The method comprises a dual level photoresist deposition technique on a semiconductor wafer, in conjunction with a double lift-off and dummy gate procedure. In the process, T-bar shaped portions of overlying top and bottom photoresist layers are produced, one of such T-bar shaped portions forming a dummy gate. Metal is then deposited on the upper surface of the T-bar shaped portions and on the exposed surface of the substrate to form a source and a drain. In a first lift-off step the metal on the T-bar shaped portions and the underlying remaining top layer portions, are removed. An inorganic film such as SiO is then deposited on the remaining bottom layer portions and over the metal on the surface of the substrate. In a second lift-off step the SiO film on the remaining bottom layer portions and the underlying bottom layer portions are removed. The space between remaining portions of the SiO film on the substrate defines a gate opening of submicron size. The metal on the surface of the substrate beneath the inorganic film is then alloyed by treatment at high temperature, and gate metal is deposited over the gate opening. Metal can then be deposited on the SiO imprinted film to form interconnects to the source and drain.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile