The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 1987
Filed:
Dec. 13, 1984
Tomoji Takada, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A master slice type LSI is constructed as a three port memory circuit in which respective cells exclusively utilized as memory circuits constituting respective memory regions can be accessed simultaneously. More particularly each cell exclusively used as a memory circuit is constituted by a flip-flop circuit including two inverters (31, 32) which are connected in parallel opposition, a single write data input line (39) and two read out data output lines (40, 41) which are connected to the flip-flop circuit through transfer gate circuits (33,34,35), respectively, and at least three word lines (36, 37, 38) along which independent word signals are transmitted. The three transfer gate circuits (33, 34, 35) are independently enabled and disenabled based on the word signals transmitted over the word lines (36, 37, 38).