The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 1987

Filed:

Oct. 11, 1985
Applicant:
Inventors:

Robert A Hartman, Chagrin Falls, OH (US);

Paul E Koch, Chagrin Falls, OH (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
29572 ; 29589 ; 29590 ; 136258 ; 136290 ; 156345 ; 20419232 ; 204298 ; 118718 ; 118719 ; 118723 ; 118724 ; 118729 ; 427 39 ; 427 74 ; 427 86 ; 4272555 ;
Abstract

A process and apparatus for continuously producing a relatively large-area, lightweight array of amorphous semiconductor alloy photovoltaic cells having no substrate includes depositing a semiconductor alloy film, such as amorphous silicon, on a travelling surrogate substrate, applying a support material to the traveling film to give it mechanical strength and separating the film and support material from the traveling surrogate substrate by exposing them to a thermal shock. The surrogate substrate is preferably an endless stainless steel band from which the deposited alloy film is repeatedly stripped and on which deposits are repeatedly made. The apparatus may include a cleaning station for cleaning the surrogate substrate after an alloy film is removed from the substrate and before another alloy film is deposited. The apparatus may provide for the deposition and patterning of a back electrode on the substrate before deposition of the alloy film to form one set of electrical interconnections for the array. The apparatus may also provide for the deposition and patterning of a transparent, electrically conducting layer on the alloy film, before application of the support material, in order to form a second set of electrical interconnections for the array. The apparatus may also apply a protective, support material to the rear of the alloy film.


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