The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 1987
Filed:
Nov. 26, 1984
Yasuo Ikawa, Tokyo, JP;
Nobuyuki Toyoda, Yokohama, JP;
Katsue Kanazawa, Yokohama, JP;
Takamaro Mizoguchi, Yokohama, JP;
Akimichi Hojo, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A gate array integrated circuit in which gate cells are each composed of a DCFL circuit using Schottky-barrier FETs. A plurality of basic gate cells is arrayed in one direction to form a basic cell array, and such basic cell arrays are arranged parallel to each other. VDD lines and GND lines are provided to apply an operating voltage to the basic gate cells. In order to stably operate the gate array integrated circuit of DCFL structure in which the logical amplitude and noise margin are small, the VDD lines and the GND lines are arranged perpendicular to each other such that the number of the basic gate cells which are connected to each of the VDD lines is larger than that of the basic gate cells which are connected to each of the GND lines. According to this layout, the potential difference (voltage drop) developed in the GND lines by operation current is reduced.