The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 1987
Filed:
Nov. 05, 1984
Applicant:
Inventors:
Nicholas C Cirillo, Jr, Minneapolis, MN (US);
Max J Helix, Bloomington, MN (US);
Stephen A Jamison, Bloomington, MN (US);
Assignee:
Honeywell Inc., Minneapolis, MN (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
29571 ; 2957 / ; 29591 ; 148-15 ; 148175 ; 148187 ;
Abstract
A self-aligned gate process for integrated circuits based on modulation doped (Al, Ga)As/GaAs field effect transistors and in which the regions on each side of the metal silicide gate are heavily ion implanted to form the low resistance regions on either side of the gate.
Cirillo, Jr, Nicholas. (1987). Self-aligned gate process for ics based on modulation doped (al,ga) (U.S. Patent No. 4662058). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4662058
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile