Computer control memory apparatus providing variable microinstruction

Abstract

Computer control memory apparatus is disclosed wherein the microinstructions may selectively have a variable bit length. A main control memory stores microinstructions having a basic length and they are read out and stored in a microinstruction register. Microinstruction prefixes are obtained from more than one source and are selectively added to the basic length microinstruction in the microinstruction register to create longer microinstructions, as needed, for controlling the operation of the computer. The microinstruction prefixes may be obtained from a secondary control memory that is addressed at the same time as the main control memory, or may be obtained from a field of N bits which is a part of a previous microinstruction read out of the main control memory and saved in an expansion register, or may be all zeroes when it is not desired to expand a microinstruction of basic length read out of the main control memory. All such microinstruction prefixes are connected via a multiplexer from their source to the portion of the microinstruction register used for prefixing them to the basic length microinstructions. In the event an interrupt occurs to obtain a higher priority string of microinstructions, the multiplexer is prevented from connecting the sources of microinstruction prefixes to the microinstruction register until the interrupt is ended.