Decoder for three level coded data

Abstract

The decoder herein described recovers the clocking and the data in a binary format from a three level coded signal. The decoder has application to data rates in excess of one half gigabits per second, which are common to optical communication channels. The decoder employs a comparator for evaluating to two bit accuracy each state of the signal, a two stage, two bit per stage shift register, and decision logic for recovering the data in a binary format. The decoder is monolithically integrated using buffered FET logic on a gallium arsenide substrate. In the decoder, the comparator is optimized by the use of three zero crossing detectors, one of which has a zero input for reference purposes, in combination with two internal voltage dividers and two external voltage references for achieving an accurate drift free determination of the levels of the three level code (TLC) signal. The clock recovery means is optimized for high speed operation by the use, in association with each transition level, of a time delay and an exclusive OR-gate, the logical design of the exclusive OR-gate entailing a four NOR-gate configuration in which the timing indication resulting from each TLC transition is propagated through a like number of states and thereby experiences the same overall propagation delay, in reaching the decoder output.