Video memory controller

Abstract

A video memory controller controls a DRAM (dynamic random access memory) used as a video memory and as a system memory. The video memory and the video memory controller are normally a part of a video system which includes a data processor, the video memory, the video memory controller, a CRT controller and a CRT display device. The video memory controller includes a row address latch for storing a row address from the data processor, a column address latch for storing a column address from the data processor, a refresh address register for storing a memory refresh address and a display update generator for sequentially generating the addresses necessary for update of the CRT display. A multiplexer couples the proper address to the video memory under control of a memory cycle generator which generates the timing of the memory refresh and display update. An arbiter device enables only one of the possible memory cycles at a time. The data processor has higher priority over memory refresh during an initial period of each horizontal line of the display, while the memory refresh has higher priority over the data processor during the final period of each horizontal line.