Field-transfer ccd imagers with poly-phase image registers, operated to

Abstract

The parallelly arranged charge transfer channels in the image register of a field transfer type CCD imager are clocked with a number of phases equal to 2m, m being a positive integer equal to two or more, during image transfer. The successive gate electrodes receiving each cycle of successive-in-time clock phases during image transfer are considered to be consecutively ordinally numbered first through 2m.sup.th. During the image integration times of odd fields, the first gate electrode in each cycle of the image register is biased to induce a potential energy barrier thereunder, and photoresponse charge is collected under the gate electrodes of the image register exclusive of each first gate electrode. During the integration times of even fields, the (m+1).sup.th gate electrode in each gate-electrode cycle of the image register is biased to induce a potential energy barrier thereunder, and photoresponse charge is collected under the gate electrodes of the image register exclusive of each (m+1).sup.th gate electrode. This provides pseudo line interlace in accordance with the invention, while minimizing the length of the potential barrier to avoid fixed-pattern partitioning noise or 'grain'.