The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 1987
Filed:
Nov. 25, 1985
Mehdi H Sani, La Jolla, CA (US);
Donald G Tipon, San Diego, CA (US);
NCR Corporation, Dayton, OH (US);
Abstract
The circuits of the present invention convert CMOS logic levels to corresponding ECL logic levels to permit the coupling of CMOS and ECL circuits. One preferred circuit embodiment is comprised of three p-channel transistors and one n-channel transistor. The first p-transistor has its source connected to a reference potential, such as ground, and its drain electrode connected to the source of the second p-transistor. The drain and the gate of the second p-transistor are connected together to an output terminal. The drain of the third p-transistor is connected to the output terminal. The gate and the source of the third p-transistor are connected to the drain of the n-transistor. The source of the n-transistor is connected to a CMOS compatible potential source. The CMOS logic level signal is coupled to the gate of the first p-transistor and the gate of the n-transistor. The output terminal is connected to an ECL compatible potential source via a termination resistor. Two other circuit embodiments are disclosed which provide for non-inverted and inverted outputs.