Clocked comparator

Abstract

A clocked comparator comprising a comparison stage (1) for comparing an analog input voltage V.sub.IN with an analog reference voltage V.sub.REF and supplying an intermediate signal V.sub.M and its complement V.sub.M, an amplifier stage ((2) for amplifying the logic states of the intermediate signal, a first latching stage (3) and a second latching stage (4) coupled to the comparison stage and to the amplifier stage respectively, for generating and storing the logic states determined by the signals from the comparison and amplifier stages. A second comparison stage (5) is coupled in parallel with the first comparison stage to compensate for hysteresis in said first comparison stage. A second amplifier stage (6) is coupled in parallel with the first amplifier stage to eliminate phase indeterminacy of the logic states of the intermediate signal. The second latching stage and the first latching stage are alternately enabled by a first clock signal C and its complement C. The first amplifier stage and the second amplifier stage are enabled alternately by a second clock signal H and its complement H. The amplifier stages operate in phase with the comparison stages and the first latching stage. Use: An analog-to-digital converter constructed by means of depletion-type gallium-arsenide field-effect transistors.