The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 1987
Filed:
Oct. 29, 1984
Arthur M Cappon, Chestnut Hill, MA (US);
Raytheon Company, Lexington, MA (US);
Abstract
A shift register comprising a plurality of memory cells serially coupled together along a signal bus. Each one of the plurality of memory cells comprises a first amplifier, fed by an input logic signal, for amplifying and inverting the logic state of the input logic signal. A first storage section is included for either enabling storage in the first storage section of an electric charge corresponding to the voltage level of the amplified and inverted input logic signal, or disabling storage in the first storage section of the electric charge, selectively in response to a first control signal. The stored electric charge is converted to an intermediate logic signal having a predetermined voltage level. Each memory cell additionally includes a second amplifier, fed by the intermediate logic signal, for amplifying and inverting the logic state of the intermediate logic signal. A second storage section is included for either enabling storage in the second storage section of an electric charge corresponding to the voltage level of the amplified and inverted intermediate logic signal, or disabling storage in the second storage section of the electric charge, selectively in response to a second control signal, the second control signal being out of phase with respect to the first control signal. The stored electric charge is converted to an output logic signal having a predetermined voltage level.