The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 1987
Filed:
May. 11, 1984
Hideharu Koike, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A full-adder circuit comprising a first node for providing an inverted summed output, a second node for providing an inverted carry output, a plurality of P channel MOS FETs connected between a Vcc terminal and the first and second nodes to form a first circuit pattern, the P channel MOS FETs being applied at the gates with an addend input signal of N-bits (N is a natural number of 1 or more) and an augend input signal of N-bits, a carry input signal of one-bit, and the one-bit inverted signals of the input signals, a plurality of N channel type MOS FETs connected between a Vss terminal and the first and second nodes to form a second circuit pattern which is substantially the same as that of said first circuit pattern, said N channel type MOS FETs being applied at the gates with the same addend, augend and carry inputs as those applied to the P channel type MOS FETs in a similar manner, a first inverter connected between the first node and a summed output terminal and for inverting a signal at the first node, and a second inverter connected between the second node and a carry output terminal and for inverting a signal at the second node.