Digital peak detecting means for a pulse train of electrical signals

Abstract

A digital peak detecting circuit for receiving a pulse train of electrical signals having a frequency within a known frequency range and for converting the same into digital signals is shown. The digital peak detecting circuit includes an input circuit having a phase-locked loop for producing clock pulses at a frequency which is a preselected integer of the electrical signals frequency and for deriving therefrom an analog input signal. A pulse control circuit receives and counts a predetermined number of clock pulses and produces count enabling signals. A peak detecting circuit is provided which includes a comparator which has the analog input signal and a analog output signal voltage applied to the inputs thereof and which has an output coupled to the pulse control circuit. A digital counting circuit is responsive to count enabling signals by changing count direction and produces discrete digital output signals which are stored in a latch register at the time the digital counting circuit changes its count direction. A digital-to-analog converter produces the analog output signal voltage and it is applied to the comparator input for comparing the analog input signal with the analog output signal voltage and the comparator enables the digital counting circuit as long as the analog input signal is of a greater magnitude than the analog output signal voltage, and when this condition is reversed, the digital counting circuit is reversed in counting direction, and the binary value thereof is stored in the latch register.