Logic data transfer bus preloading circuit

Abstract

A data transfer bus preloading circuit including a large sized transistor r ensuring rapid bus conductor preloading. This transistor is conductive at the beginning of the preloading step proper, but is blocked as the bus voltage reaches the desired preload value which corresponds to the sum of the respective threshold voltages of two other transistors of the circuit. The circuit includes five field effect transistors, two supply terminals, a preloading control input terminal and a preloading inhibiting input terminal. The large size transistor is connected between a first supply terminal and the output terminal of the circuit. A second transistor is connected between the gates of the first and third transistors. The gate of the second transistor is connected to the preloading control input terminal. The third transistor is connected between the source terminal and the fifth transistor. The gate and source of the third transistor are connected together. The fourth transistor is connected between the ground supply terminal and the gate of the first transistor. The gate of the fourth transistor is connected to the preloading inhibiting input terminal. The fifth transistor is connected between the third transistor and the ground supply terminal. The gate of the fifth transistor is connected to the output of the circuit. It is also possible to add a sixth transistor between the fifth transistor and the ground supply terminal with the drain and gate of this transistor being connected together.