Interface circuit having a shift register inserted between a data

Abstract

An interface unit for connecting a transmitting unit to a receiving unit, the transmitting being capable of transmitting data at a speed greater than the processing speed of the receiving unit. The interface includes a serially connected multistage register which receives input data from the transmitting unit at its input stage and reads out data stored in its output stage to the receiving unit. It also includes a control circuit and a counter storing a count corresponding to the quantity of data stored in the register, the counter being incremented by one each time data is added to the register and decremented by one each time data is read from the register output stage. The control circuit is composed of a decoder and write control circuit. The decoder provides a signal to the write control circuit indicative of the count in the counter. When a datum is to be received from the transmitting unit, it signals the interface through a gate circuit, this signal incrementing the memory. This increment is sensed by the decoder which enables the write control circuit to cause the input data to be written into the first available register stage closest to the output stage. When the register is full, this information is provided to the transmitting unit by the decoder to inhibit the generation of additional data to the interface until an empty stage is available in the register.