The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 1987
Filed:
Feb. 12, 1985
Rituparna Shrivastava, Fremont, CA (US);
Raymond E Bloker, Campbell, CA (US);
Fred B Jenne, Los Gatos, CA (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
A CMOS semiconductor device which avoids latchup in the powerup mode as well as in the normal operating mode is provided. The device is provided with an on-chip back bias generator which greatly reduces the possibility of forward biasing parasitic NPNP transistors in normal operation. During the powerup mode, before the backbias voltage becomes effective, a clamp diode provided in integrated form outside a guardring surrounding the circuit elements is effective to clamp a large negative voltage that may be created by a 'hot-socket' connection to an output. In a modified form of the invention, a junction field effect transistor is provided to prevent forward biasing of the parasitic transistors in a somewhat different manner.