The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 1987

Filed:

Jun. 29, 1984
Applicant:
Inventors:

Mei Hsu, Sunnyvale, CA (US);

Thomas H Wong, Sunnyvale, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03L / ;
U.S. Cl.
CPC ...
307455 ; 307475 ; 307264 ;
Abstract

An emitter coupled gate circuit for providing both a full output voltage swing and a fractional output voltage swing with an adjustable high level output voltage includes a single differential transistor circuit having a first current switch transistor and a second current switch transistor and a single constant-current source. A first load resistor has its one end connected operatively to the collector of the second current switch transistor. A second load resistor has its one end connected operatively to the collector of the second current switch transistor, and a level shifting resistor has its one end connected to the other end of the second load resistor. A first emitter follower transistor has its base connected to the one end of the first load resistor and its emitter connected to an upper-level full output voltage swing terminal. A second emitter follower transistor has its base connected to the one end of the second load resistor and its emitter connected to an upper-level fractional output voltage swing terminal. The upper-level fractional output voltage swing terminal has an adjustable high level output voltage which is controlled by the ratios of the resistance values of the level shifting resistor relative to the first load resistor and the second load resistor.


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