The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 1987
Filed:
Sep. 04, 1984
Applicant:
Inventor:
Masaru Uya, Hirakata, JP;
Assignee:
Matsushita Electric Industrial Co., Ltd., Kadoma, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307243 ; 307443 ; 307451 ; 307279 ;
Abstract
In a high speed latching circuit (C) for selectively receiving one or plural slowly changing input data signals and latching them at high speed, one or plural first CMOS FETs (31, 33, 35, 37) and one or plural second CMOS FETs (32, 34, 36, 38) of p-conductivity type are connected in series respectively to form one or plural series connections (31+32, 33+34, 35+36, 37+38), wherein selection signals are given to the gates of the first CMOS FETs, input data signals are given to the gates of the second CMOS FETs and a flip-flop (30+39+41) is driven by selected one of the series connections.