Multi-format binary coded decimal processor with selective output

Abstract

Digital circuitry performs arithmetic operations upon first and second binary coded decimal digit strings input thereto. The digital circuitry provides for receiving and storing a first and second BCD digit, the digits having an arbitrary data type format. The first and second data types are selected from the group of packed and unpacked data. The circuitry then performs the arithmetic operation upon the stored BCD digits to obtain a result data word which is made available in a data type format corresponding to a selected one of the input BCD digits. In a particular embodiment, a plurality of the circuits can be operated in a digit slice structure. The digit slice structure operates upon strings of packed, unpacked, and mixed data type arithmetic operands and provides, at its output lines, output data in a format corresponding to a selected input data type. In particular, a unique interconnection of the plural output lines of the circuitry enables the output data type to be packed or unpacked as desired. The circuitry also provides for automatic selection of digits applied to the circuitry thereby relieving the operating environment from significant time consuming and costly supervision.