Line fault tolerant synchronous timing reference generator for static

Abstract

A timing reference generator for producing a multi-phase timing reference signal in synchronism with a multi-phase source voltage signal is disclosed. The timing reference generator uses an N stage array of series connected phase-locked loop (PLL) circuits to preserve the prefault condition of an input source signal by open circuiting at least the Nth stage prior to the propagation of the fault condition signal through the array. The open circuited stage acts like a flywheel to preserve the prefault condition of the source signal. This output can be used to replace the lost source signal until the fault condition has cleared. The output of the first PLL is used to provide the timing reference signals. This arrangement allows for sensing delays in establishing the occurrence of a fault and the consequent delay in activation of the flywheel. The first PLL comprises a positive sequence type phase detector and series connected band reject harmonic filters in order to eliminate phase errors caused by input voltage unbalance and input harmonic content. Subsequent PLL circuits are of the zero phase error type. Multiple faults are tolerated if two stages of the array are connected in parallel and alternately operated as flywheels. The flywheels are sequenced so that one is kept operating as a flywheel while the other one settles.