The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 1987

Filed:

May. 17, 1985
Applicant:
Inventors:

Naohiro Matsukawa, Kamakura, JP;

Sigeru Morita, Tokyo, JP;

Hiroshi Nozawa, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; H01L / ;
U.S. Cl.
CPC ...
2957 / ; 29571 ; 148-15 ; 148187 ; 148D / ; 357 2312 ; 357 2314 ; 357 91 ;
Abstract

A method of manufacturing a nonvolatile semiconductor memory device having a gate oxide layer including a relatively thin silicon dioxide layer. This gate oxide layer including the thin silicon dioxide layer is formed by the steps of forming the gate oxide film on a semiconductor element region in a silicon substrate; removing a portion of the gate oxide film to expose a portion of the silicon substrate; implanting impurity ions in the exposed portion of the substrate to an extent that a peak concentration of the impurity ions exceeds a solid solution limit at a temperature of the following thermal annealing step; activating the implanted impurity by thermal annealing so as to form a high impurity concentration layer and thermally oxidizing a surface of the high impurity concentration layer to form the thin silicon dioxide layer.


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