Floating gate type eeprom with a substrate region used for the control

Abstract

A semiconductor memory device having a floating gate transistor and an insulated gate transistor, is provided a p-type semiconductor substrate, first, second and third semiconductor regions which are formed in the surface area of the substrate, a floating gate electrode capacitively coupled through a first insulating layer to a current path including the first and second semiconductor regions, a control gate electrode capacitively coupled through a second insulating layer to the floating gate electrode, and an insulated gate electrode which is formed through a first insulating layer on that portion of the substrate which lies between the second and third semiconductor regions. The first insulating layer of the semiconductor memory device is formed on that portion of the substrate which lies between the first and second semiconductor regions. The control gate electrode is a fourth semiconductor region which is formed in the surface area of the substrate. A second insulating layer is formed of a very thin monocrystalline oxide layer, and is formed on the fourth semiconductor region. The current path of the floating gate transistor is perpendicular to that of the insulated gate transistor substantially in the same plane.