The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 1987
Filed:
Sep. 26, 1984
Applicant:
Inventor:
William S Carter, Santa Clara, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307465 ; 307303 ; 307468 ;
Abstract
A special interconnect circuit which connects adjacent configurable logic elements (CLEs) in a configurable logic array (CLA) without using the general interconnect structure of the CLA. In one embodiment, an array of CLEs is arranged in rows and columns and a special vertical lead circuit is provided which connects an output lead of a given CLE in a given column to a selected input lead of the CLE above it and below in the same column. Special horizontal lead circuits are provided which connect a given output lead of a given CLE to a selected adjacent input lead of the CLE in the same row.
Published as:
EP0177261A2; JPS61198919A; US4642487A; EP0177261A3; CA1248597A; EP0177261B1; DE3580642D1; JPH06283996A; JPH08107347A; JPH08204543A; JPH09261040A; JPH09261039A; JP2718006B2; JP2873997B2; JPH11317659A; JP3002425B2; JP3083813B2;