Source-side self-aligned gate process

Abstract

A self-aligned gate GaAsFET fabrication process and structure are disclosed in which the gate metallization is offset to one side of the channel aligned with the source-side implant. The arrangement is advantageously provided by a photolithographic fabrication process in which a pair of self-aligned implants are made, before gate metallization. As an intermediate step, a first etch-resistant ZrO patch is deposited over at least one of the self-aligned implants aligned therewith. Then, a second such patch is deposited which overlaps the other self-aligned implant and extend a distance over the channel between the two implants. The first and second patches are thereby spaced closer together (e.g., 0.5 .mu.m) than the implants (e.g., 1.0 .mu.m). The patches fix the gate length at less than implant spacing and offset the gate metallization along the source-side self-aligned implant, away from the drain implant. The gate is preferably recessed. This arrangement effectively provides asymmetrical doping concentrations on opposite sides of the gate conductor, which enables improvement in both gate-drain capacitance C.sub.gd and source-gate resistance R.sub.s.