The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 1987

Filed:

May. 21, 1984
Applicant:
Inventors:

Robert A Dwyer, Readington Township, Hunterdon County, NJ (US);

Russell G Ott, Cranford Township, Union County, NJ (US);

Assignee:

RCA Corporation, Princeton, NJ (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364900 ;
Abstract

A universal interface adaptor circuit (UIAC) for connecting any one of a plurality of either of two general microprocessor types to a peripheral device using the same interface connections to selectively generate and supply either a WRITE ENABLE signal or a READ ENABLE signal to a peripheral device. A first of the two general types of microprocessors is used in multiplexed-bus multiprocessor (MBM) systems and the second of the two general types of microprocessors is used in non-multiplexed-bus microprocessor (NMBM) systems, where the microprocessors used in both the MBM and the NMBM systems each supply three output signals for determining whether the function is a READ or a WRITE function and the time of occurrence of such READ or WRITE function. The UIAC comprises logic array having three input terminals X, Y, and Z for receiving the three output signals from each of the microprocessors employed in either the MBM systems or the NMBM systems. First selected logic elements of the logic array respond to the three output signals received from the MBM type systems to produce a READ ENABLE signal when the signals thereon indicate a READ function and a WRITE ENABLE signal when the signals thereon indicate a WRITE function, and second selected logic elements of the logic array respond to the three output signals received from the NMBM type systems to produce a READ ENABLE signal when the signals thereon indicate a READ function, and to produce a WRITE ENABLE signal when the signals thereon indicate a WRITE function.


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