The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 1987

Filed:

Jul. 02, 1984
Applicant:
Inventor:

Mark S Birrittella, Phoenix, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H01L / ;
U.S. Cl.
CPC ...
307454 ; 357 36 ; 357 46 ; 357 92 ;
Abstract

A logic circuit is provided having increased flexibility, increased package density over I2L circuits and improved noise immunity over ISL circuits. A first NPN multi-collector transistor has its collectors coupled wherein each provide an output signal, and a base connected to an input terminal and to the base of a second NPN transistor. The emitter of the second transistor is coupled to receive a first supply voltage, typically ground. The input terminal is coupled to a second supply voltage by a resistor. When monolithically integrated, the emitter and collector of the first and second transistor, respectively, share a common buried epitaxial layer that does not require contact with a metallization layer.


Find Patent Forward Citations

Birrittella, Mark. (1987). Complex direct coupled transistor logic (U.S. Patent No. 4641047). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4641047

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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