The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 1987
Filed:
Nov. 28, 1984
Surinder Krishna, Fremont, CA (US);
Fairchild Semiconductor Corporation, Cupertino, CA (US);
Abstract
A method for producing an improved capacitor in MOS technology utilizing a thin layer oxide dielectric to improve the active/parasitic capacitance ratio while maintaining a high breakdown voltage and a low leakage current. A polycrystalline silicon layer is formed over a silicon dioxide field region on a wafer of semiconductor silicon. Phosphorus ions are implanted in the polycrystalline silicon layer at an implant energy between approximately 80 and 100 keV. The surface of the polycrystalline silicon layer is oxidized to form an interpoly oxide, utilizing an oxidation temperature which, for the implant dosage of phosphorus ions used, is sufficient to make the interpoly oxide layer approximately 770 Angstroms thick. The structure is then annealed at a temperature of approximately 1100.degree. C. in oxygen and HCl. A second polycrystalline silicon layer is formed over the interpoly oxide layer, and the process completed in the conventional manner.