The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 1987
Filed:
Feb. 08, 1985
Ian Crossley, Andover, MA (US);
Daniel Donoghue, Tewksbury, MA (US);
Steven Mittleman, Framingham, MA (US);
Seth Nash, Boston, MA (US);
Alpha Industries, Inc., Woburn, MA (US);
Abstract
A hybrid ring mixer includes an annular conducting ring on a gallium arsenide substrate coated on the bottom with a conducting layer to comprise a strip transmission line. Three conductors spaced by 120.degree. extend radially outward from the annular ring to define local oscillator, signal input and i-f ports, respectively. A pair of conductors spaced by substantially 120.degree. extend radially inward to comprise diode ports. A conducting surface inside the annular ring is grounded and has circular sectors of different radius bounded by radii extending from the center of the ring and bisecting the signal and local oscillator ports, respectively. The sector of larger radius is located in the 120.degree. sector between the signal and local oscillator ports. Mesa diodes are connected between each of the diode ports and the sector of smaller radius. A via opening surrounded by a conducting layer extends between the bottom and top of the substrate to establish conducting contact between the bottom conducting layer and the grounded conducting surface. The circuit is formed by diffusing n+ and n epitaxial layers into the substrate, etching through the end layer and depositing a cathode ohmic contact on the n+ layer, establishing an anode contact on the n layer, metalizing the substrate upper surface to form the circuit, etching through the bottom of the substrate to form the via opening and plating the back side of the substrate and the region around the via opening.