The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 1987
Filed:
Jun. 05, 1984
Shlomo Margalit, Pasadena, CA (US);
Amnon Yariv, San Marino, CA (US);
Zeev Rav-Noy, Los Angeles, CA (US);
California Institute of Technology, Pasadena, CA (US);
Abstract
High transconductance vertical FETs are produced in III-V epitaxially grown layers doped n, p and n, with the in-between submicron (0.15 .mu.m) layer serving as the FET channel. The layer on the drain side of the channel may be thicker (3 .mu.m) than on the source side (1.5 .mu.m). The structure is V-grooved to expose a nearly vertical surface that is Si implanted or regrown with graded n-type GaAs/GaAlAs before a gate contact is deposited on the vertical structure. An alternative to employ a heterostructure with GaAlAs layers for the source and drain, and GaAs for the channel layer. Graded GaAs/GaAlAs is then selectively regrown in the channel layer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile