The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 1987
Filed:
Mar. 09, 1984
Shigeru Kuroda, Hadano, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A method of manufacturing a GaAs semiconductor device of an E/D construction having a GaAs/AlGaAs heterojunction and utilizing two-dimensional electron gas, which includes the steps of forming a heterojunction semiconductor substrate and etching a portion of the substrate to provide a gate portion of a depletion-mode FET. When the substrate of a semi-insulating GaAs layer, an undoped GaAs, an N-type AlGaAs layer providing an electron-supply layer, and a GaAs layer is formed, the GaAs layer is composed of a first GaAs layer, an etching stoppable AlGaAs layer, and a second GaAs layer, the first GaAs layer being formed on the N-type GaAs layer. The etching for provision of the gate portion is carried out by a dry etching method using an etchant of CCl.sub.2 F.sub.2 gas, so that the second GaAs layer can be etched but the AlGaAs layer cannot be etched. Thus, the thickness of the layers between a gate electrode of the depletion-mode FET and the GaAs/AlGaAs heterojunction plane is determined by the formation of the heterojunction substrate, and consequently a better uniformity of the threshold voltage of depletion-mode FETs is obtained.