The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 1987
Filed:
May. 17, 1984
Richard F Herlein, San Jose, CA (US);
Fairchild Semiconductor Corporation, Cupertino, CA (US);
Abstract
A formatting circuit for a high speed integrated circuit test system controls the application of timed data pulses to the input terminals of the device being tested, generates strobe signals to control comparators connected to the output terminals of the device being tested, and provides circuitry to decode error signals received from the device being tested. The formatting circuit routes all critical signal paths to the device under test over separate signal lines, thereby allowing compensation for the different propagation delay of each signal path. The input transitions and output strobe signals for the device being tested are not fixed in time with respect to the system clock, but are referenced to it. This enables drive data cycles and compare data cycles to be less dependent on the system clock, and permits them to overlap and cross test period boundaries. Multiple test vectors for a given test period are permitted and error correlator decodes error signals produced by incorrect output signals from the device under test. The error correlator decodes these error signals and logs them in a memory location corresponding to the proper test vector.