The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 1986
Filed:
Sep. 19, 1983
S Robert Perera, Boulder County, CO (US);
Michael J O'Keeffe, Boulder County, CO (US);
Storage Technology Partners II, Louisville, CO (US);
Abstract
A self-checking shared encoder/decoder circuit for use with a Reed-Solomon coding scheme of an optical disk storage system. The optical disk system includes a drive adapted to permanently store data on a removable platter. Prior to recording a data byte on the platter, the data is encoded with a Reed-Solomon code. When the data is read from the disk, it is decoded and error correction syndromes are generated. A plurality of syndrome buffer registers are provided in order to allow several of the error correction functions to be carried out in parallel. Syndromes that are detected to comprise all zeros are used to simplify the error correction processes beyond the normal processes used. The same circuitry is shared for performing the encoding and decoding functions. This circuitry includes independent sets of a RAM, coupled to one input of an exclusive OR (modulo two sum) adding circuit. The output of the adding circuit is fed back to an input of the RAM. Two multiplier circuits are coupled to the output of the RAM. A product of one is tied to one input of the modulo two addition circuit. The product of the other is combined with similar products from other sets, and the resulting combination signal is selectively connected to the other input of the modulo two addition circuit, along with data to be recorded on the platter, or data read from the platter.