Vector processor system comprised of plural vector processors

Abstract

An array processor includes a central vector processing unit including a plurality of vector registers and a pipe-line control arithmetic and logical operation unit (ALU) operative to execute an instruction (vector instruction) requiring vector processing, and a plurality of vector processing units including a plurality of vector registers and a pipe-line control ALU operative to execute an instruction (array instruction) requiring array processing. The central vector processing unit fetches and decodes the vector instruction or the array instruction to execute the decoded instruction, when this instruction is a vector instruction, but operates to start the vector processing units when the decoded instruction is an array instruction. Each of the vector processing units executes that operation to one of plural vector data comprising array data to be an object of the operation designated by the decoded instruction, which is designated by the instruction for one of the vector data, when the decoded instruction is an array instruction. When the result of the operation designated by the array instruction is vector data, each of the vector processing units computes and stores one element of vector data in built-in scalar registers, and sends out that element to the central vector processing unit so that the element may be stored in vector registers in the central vector processing unit. When the result of the operation designated by the array instruction is array data, each of the vector processing units computes and stores one vector data of those resultant array data in built-in vector registers.