The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 1986

Filed:

Feb. 26, 1985
Applicant:
Inventor:

Anand Upadhyay, Rockford, IL (US);

Assignee:

Sundstrand Corporation, Rockford, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H / ;
U.S. Cl.
CPC ...
363 56 ; 363 98 ; 363132 ;
Abstract

Prior circuits for protecting inverter switches from the possibility of overlapping operation which may cause shoot-through have required complex and expensive delay circuits to provide a fixed delay between turn-off of one switch and turn-on of the complementary switch. In order to overcome the problem of complexity and expense, a protection circuit according to the present invention includes a drive signal source for developing complementary first and second drive signals and first and second drive logic circuits coupled to the drive signal source for controlling first and second switching devices, respectively, in response to the drive signals so that overlapping operation is prevented. Each of the drive logic circuit includes an inhibit logic circuit having first and second inputs which receive the drive signal and an inhibit signal developed by the other drive logic circuit, respectively. The inhibit logic circuit generates a control signal to turn on the respective switching device only when the drive signal is present and the inhibit signal from the other drive logic circuit is not present. Circuits are included for generating the inhibit signal that is coupled to the inhibit logic of the other drive logic circuit, such inhibit signal being generated during the time that the control signal is generated and for a predetermined time period thereafter so that the complementary switch is maintained in an off state until the predetermiend time period has elapsed.


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