Circuit arrangement for post-detection suppression of spurious radar

Abstract

A radar, e.g. as used for the surveillance of aerial navigation, has a receiver feeding incomimg echo signals to several Doppler filters in parallel, the output signal of each filter beign passed to a utilization stage through a respective attenuator connected to the filter output in parallel with an associated area processor. The latter comprises a pulse counter synchronized with the scanning motion of the radar antenna to register the number of echoes received in successive sweeps from different zones into which the surveyed space is divided in distance and azimuth. Upon the last sweep of a sector encompassing a group of such zones, the contents of respective cells of a sector memory loaded by the pulse counter are compared with a first threshold. If the number of echoes stored in such a cell exceeds that threshold, a count written in an assigned cell of a scan memory is incremented; if it does not, the count is decremented. A delayed reading of the scan memory, during a subsequent antenna rotation, determines the setting of the associated attenuator during the sweep of any zone. The attenuator includes a delay line from which the signal amplitudes appearing in the output of the corresponding Doppler filter during recurrent sweeps of the same zone are simultaneously recovered and averaged; the result is multiplied by a factor selected by comparison with a second threshold in the associated area processor on the basis of the numerical value read out from the corresponding cell of the scan memory.