The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 1986
Filed:
Sep. 14, 1984
Andrew M Mallinson, Salem, NH (US);
Ferranti plc, Cheshire, GB;
Abstract
A bipolar transistor logic circuit has a hierarchical arrangement of pairs of bipolar transistors, each pair of transistors having their emitters connected together, and the bases of at least some pairs receiving a differential input to the logic circuit. The highest level has only one pair of transistors, with their emitters connected to a constant current source. A differential output is provided on two lines, at least the collectors of the lowest level being coupled selectively to the lines. The arrangement is required to be symmetrical. In an otherwise non-symmetrical arrangement, the arrangement is made symmetrical by including dummy pairs of transistors not receiving a differential input. In performing a logical operation, the differential output, and the collector potentials of each pair of transistors start to vary in the appropriate sense. Further, there is a switch controlling the constant current source enabling the logic circuit to be driven ON and OFF so that the logic circuit starts each operation in the equilibrium condition. Hence the logic circuit is fast in operation. In one embodiment, the logic circuit also includes a latch having two parallel arms, each arm including an input transistor coupled to the hierarchical arrangement, and a switching transistor. The switching transistor collectors and bases are cross-coupled, and the emitters are connected together and to two parallel constant current sources. The output of one source is insufficient to drive the latch, but is sufficient to set the latch. The output of the other source is sufficient to drive the latch, and is connected to the switching transistors via controlled by timing means common also to the switch associated with the hierarchical arrangement.